Plunify was founded in Q4 2009 to develop a cloud computing application platform that enables semiconductor chip designers to shorten time-to market and reduce development costs with no disruption to existing workflows. The company is currently focused on design and timing closure for FPGAs. Plunify is headquartered in Singapore with a business development office in Sunnyvale, California.
In Q1 2011, Plunify was awarded up to S$500,000 in seed funding from SPRING Singapore’s Technology Enterprise Commercialization Scheme (TECS). In October 2012, Plunify was awarded S$589,000 in incubation financing and support from Singapore based Get2Volume, co-funded by the Singapore National Research Foundation.
Plunify has developed a secure, scalable and easy-to-use cloud computing platform to accelerate semiconductor chip design. By providing optimization algorithms, on-demand compute resources, software tools and IP modules, Plunify’s platform enables chip design companies to accelerate time-to-market and reduce development costs. Plunify’s technology enables parallel processing of processes like simulation, synthesis and place-and-route, and selective offloading to minimize latency for interactive designs.
The cloud-based platform is based on Amazon Web Services’ cloud computing infrastructure. Through 256-bit AES encryption, asymmetric key pair authentication and SSL transmission techniques, Plunify ensures data security at levels comparable to that offered by semiconductor foundries.
Plunify’s EDAxtend platform simplifies the complexities of cloud computing and supports a set of APIs built specifically for chip design workflows. By providing an eco-system of tools and IP, catering to the different stages of chip deign workflows, Plunify removes the overhead of accessing the cloud for chip design companies. Working with design and verification tool vendors, Plunify also helps partners get their products to market rapidly, and makes best-in-class tools and IP available in an integrated platform.
Three clients are currently available for the EDAxtend platform.
Explorer++ is an extension to Xilinx ISE SmartXplorer to help engineers with timing closure. Existing tools approach timing issues by trying different implementation parameters and strategies. Explorer++ provides scalable, on demand servers and Plunify-customized timing strategies.
FPGAAccel Web is a browser-based interface that provides a full FPGA design compilation environment online for Altera FPGAs and PLDs.
FPGAAccel Client is a plugin that enables companies with established tools to access the cloud to run compute intensive processes without disrupting workflows. The FPGAAccel cloud-based FPGA timing closure solution for Altera’s Quartus II software offloads CPU- and memory-intensive FPGA design tasks to Plunify’s managed cloud, running multiple synthesis and place-and-route iterations in parallel to meet clock frequency targets, potentially reducing days of effort into a few hours. The Cloud Closure feature calculates relevant timing parameters before distributing synthesis and place-and-route tasks across multiple servers in a managed cloud computing network.
The FPGAAccel™ solution is delivered via a desktop plugin for Quartus II and integrates seamlessly with existing FPGA workflows. Integrated directly with major FPGA software tools, the FPGAAccel client does not require a steep learning curve and needs only a working Internet connection. Tasks like synthesis and place-and-route can be selectively sent for remote processing. Because local resources are freed up, the FPGAAccel client can also be used when traveling or at a remote site.
Plunify and Sigasi nv, a supplier of tools for hardware design, have formed a joint collaboration to enable Electrical Engineering students and researchers at the National University of Singapore greater ease of use and security in how they develop ICs. Previously, the only available means for running digital logic simulations was to spend hours downloading and installing a multigigabyte software package, which is time-consuming, error-prone and also requires significant disk space, CPU and memory on the user’s computer. The combined solutions uses Sigasi’s VHDL editor with type-time compile, providing immediate feedback, integrated with Plunify’s Cloud Compile™ remote simulation and compilation platform.
According to Plunify, development and test workflows used by engineers make up a $5B market, of which approximately $360M belongs to embedded systems design and $900M to FPGA design. Plunify argues that its platform provides 30x – 100x improvement in design time for compute intensive design phases, based on its algorithms and scalable resources. Future version will add capabilities such as design exploration, regression testing, team collaboration, and a design marketplace. The company currently has 500+ beta users in 48 countries, and has a ‘pay as you go’ access model.