Hardware design teams need to see if an existing design works when different parameters are applied, for example different FPGA software tool versions or changes in adjacent non-FPGA modules. Such regressions involve running multiple test vectors to quickly detect if something broke as a result of the changes.
Plunify helps design engineers set up and execute regression workflows to evaluate many different scenarios.
Analyzing critical paths, modifying a design and re-compiling are critical, iterative steps in getting a design to meet timing. Both the design engineer’s expertise and short build turnaround times are critical in solving problems.
Plunify helps design engineers execute and analyze multiple timing closure attempts in parallel, speeding up design closure efforts.
Reducing power, increasing maximum frequency, lowering area utilization are optimization goals that design engineers aim for after getting a design to work. Changes in timing may have effects on area or power so balancing tradeoffs while maximizing primary objectives is a priority.
Experimenting with different FPGA software tool options or vary the clock logic in RTL.
In the initial stages of a design, hardware decisions have not been finalized, and design engineers may want to explore different device families, speed grades and IP modules parameters. The results of these evaluations affect how the product is tested and deployed eventually.
Set up and run such experiments in parallel to gather data and make informed decisions.
Insufficient servers / licenses and packed job queues are IT factors that cause delays, which are exacerbated during periods of peak demand when everyone is trying to run builds.
Plunify helps design teams manage and scale compute demands, providing FPGA synthesis and place-and-route on a pay-as-you-use basis, alleviating concerns about IT over-investment and under-investment.